Decoupling capacitors have traditionally been located in close proximity to an integrated circuit to provide instantaneous current to the integrated circuit. For example, a digital circuit, such as a microprocessor, includes numerous transistors that alternate between dormant and switching states. Such digital circuits thus make abrupt current demands when a large number of transistors switch states. Decoupling capacitors may provide additional power to these digital circuits when needed and may recharge at a later time when power demand subsides. A power supply, such as a switching power supply, cannot accommodate the abrupt power demands from the digital circuits. The decoupling capacitor helps support the power supply voltage delivered to the digital circuits. Without a decoupling capacitor, the power supply voltage to the digital circuits would then sag unacceptably during abrupt power demands by the microprocessor. But the decoupling capacitor can supply such instantaneous power demands. In this sense, the decoupling capacitor decouples the power supply from the abrupt power demands from the digital circuits.
As the clocking rates increase, the effectiveness of a decoupling capacitor depends on more than just its capacitance. For example, a decoupling capacitor may have a relatively large amount of capacitance yet offer poor decoupling performance in the higher frequency regimes if the decoupling capacitor has unacceptably high amounts of parasitic inductance and resistance with respect to its coupling to the digital circuits it helps power. Indeed, a decoupling capacitor could have infinite capacitance yet offer poor performance in the higher frequency regimes if it also has significant parasitic inductance and resistance. This parasitic inductance and resistance depends upon a number of factors, including the distance between the decoupling capacitor and the digital circuits it helps power. To minimize this distance, the decoupling capacitor could be integrated into the die. But such integration onto the die uses expensive die real estate. An alternative is to mount the decoupling capacitor on the circuit board but then the separation between the decoupling capacitor and the die is too large such that there is then too much parasitic inductance and resistance. It is thus often preferable to use an embedded package substrate (EPS) capacitor as the decoupling capacitor. The EPS capacitor, as implied by its name, is embedded in the package substrate and is thus relatively close to the associated die on the package substrate. In this fashion, EPS capacitors offer attractively low levels of parasitic inductance and resistance compared to locating the decoupling capacitor on the board. Moreover, EPS capacitors are less expensive as compared to integrating the decoupling capacitor into the die.
EPS capacitors are embedded into the package substrate by first cutting a hole in a core substrate to form a cavity and then securing the EPS capacitor in the package substrate cavity with adhesive. The remainder of the cavity may then be filled with dielectric material. One or more substrate package metal layers may then be deposited over the EPS capacitor. Vias form electrical connections between the overlaying package substrate metal layer(s) and the EPS capacitor. An example conventional package substrate 100 is shown in FIG. 1 with an EPS capacitor 150. EPS capacitor 150 includes a positive electrode 152 and a ground electrode 154 at which electrical power of the EPS capacitor 150 may be accessed.
An M1 metal layer 160 overlays EPS capacitor 150. Via 116 forms the electrical connections between M1 metal layer 160 and positive electrode 152. Similarly, via 118 form the electrical connections between M1 metal layer 160 and negative electrode 154. For illustration clarity, positive electrode 152 is shown coupling to just one via 116. However, multiple vias 116 may couple to positive electrode 152. The number of vias 116 coupling to positive electrode 152 is limited by the footprint for electrode 152 and the required pitch or spacing between adjacent vias 116. A similar limitation exists for the number and location of vias 118 for negative electrode 154. These limitations on the number and distribution of vias 116 and 118 adversely affect the parasitic inductance and resistance for EPS capacitor 150. For example, the footprints for positive electrode 152 is relatively small such that only a relatively small number of vias 116 may couple to it as limited by the required pitch between vias 116. The number of vias 118 are limited analogously. Each via 116 and 118 must then carry a relatively large amount of current, which increases the parasitic inductance. Moreover, because vias 116 and 118 are limited to the footprints for electrodes 152 and 154, the routing flexibility in M1 metal layer 5 160 is reduced accordingly.
Accordingly, there is a need for semiconductor package substrates with embedded capacitors having reduced parasitic inductance and resistance and increased routing flexibility.